{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10515955","patent":{"patent_number":"US-10515955","title":"Methods of manufacturing transistor gate structures by local thinning of dummy gate stacks using an etch barrier","assignee":null,"inventors":[],"filing_date":"2018-05-29T00:00:00.000Z","publication_date":"2019-12-24T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"Example embodiments relating to forming gate structures, e.g., for Fin Field Effect Transistors (FinFETs), are described. In an embodiment, a structure includes first and second device regions comprising first and second FinFETs, respectively, on a substrate. A distance between neighboring gate structures of the first FinFETs is less than a distance between neighboring gate structures of the second FinFETs. A gate structure of at least one of the first FinFETs has a first and second width at a level of and below, respectively, a top surface of a first fin. The first width is greater than the second width. A second gate structure of at least one of the second FinFETs has a third and fourth width at a level of and below, respectively a top surface of a second fin. A difference between the first and second widths is greater than a difference between the third and fourth widths."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Methods of manufacturing transistor gate structures by local thinning of dummy gate stacks using an etch barrier","description":"Example embodiments relating to forming gate structures, e.g., for Fin Field Effect Transistors (FinFETs), are described. In an embodiment, a structure includes first and second device regions compris","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10515955","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10515955","citation_suggestion":"Patentable. \"Methods of manufacturing transistor gate structures by local thinning of dummy gate stacks using an etch barrier\" (US-10515955). https://patentable.app/patents/US-10515955","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10515955","json":"https://patentable.app/api/llm-context/US-10515955","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T09:40:54.065Z"}