{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10517471","patent":{"patent_number":"US-10517471","title":"Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects","assignee":null,"inventors":[],"filing_date":"2017-09-18T00:00:00.000Z","publication_date":"2019-12-31T00:00:00.000Z","cpc_codes":["A61B","A61B","A61B","H01L","H01L","H01L","H01L","H04N","H04N","H04N","H04N","H04N","H01L","H01L","H04N"],"num_claims":18,"abstract":"Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects","description":"Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked s","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10517471","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10517471","citation_suggestion":"Patentable. \"Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects\" (US-10517471). https://patentable.app/patents/US-10517471","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10517471","json":"https://patentable.app/api/llm-context/US-10517471","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T13:45:34.622Z"}