{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10521113","patent":{"patent_number":"US-10521113","title":"Memory system architecture","assignee":null,"inventors":[],"filing_date":"2017-12-20T00:00:00.000Z","publication_date":"2019-12-31T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":6,"abstract":"An embodiment includes a module, comprising: a memory bus interface; circuitry; and a controller coupled to the memory bus interface and the circuitry, and configured to: collect meta-data associated with the circuitry; and enable access to the meta-data in response to a memory access received through the memory bus interface."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory system architecture","description":"An embodiment includes a module, comprising: a memory bus interface; circuitry; and a controller coupled to the memory bus interface and the circuitry, and configured to: collect meta-data associated ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10521113","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10521113","citation_suggestion":"Patentable. \"Memory system architecture\" (US-10521113). https://patentable.app/patents/US-10521113","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10521113","json":"https://patentable.app/api/llm-context/US-10521113","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T22:39:51.164Z"}