{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10521137","patent":{"patent_number":"US-10521137","title":"Storage device array integration of dual-port NVMe device with DRAM cache and hostside portion of software stack system and method","assignee":null,"inventors":[],"filing_date":"2017-10-31T00:00:00.000Z","publication_date":"2019-12-31T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":14,"abstract":"A method, computer program product, and computer system for receiving, by a computing device, a write I/O to a storage device array coupled to a cache, wherein the write I/O may be received from a host. A cache miss in the cache may be determined for the write I/O. One or more free pages may be allocated at an address in the cache to store data for the write I/O. The address in the cache to store the data may be sent to a hostside portion of a software stack in the storage device array. The data may be written directly from the hostside portion to the cache at the address."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Storage device array integration of dual-port NVMe device with DRAM cache and hostside portion of software stack system and method","description":"A method, computer program product, and computer system for receiving, by a computing device, a write I/O to a storage device array coupled to a cache, wherein the write I/O may be received from a hos","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10521137","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10521137","citation_suggestion":"Patentable. \"Storage device array integration of dual-port NVMe device with DRAM cache and hostside portion of software stack system and method\" (US-10521137). https://patentable.app/patents/US-10521137","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10521137","json":"https://patentable.app/api/llm-context/US-10521137","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T10:40:22.276Z"}