{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10521390","patent":{"patent_number":"US-10521390","title":"Systems and method for mapping FIFOs to processor address space","assignee":null,"inventors":[],"filing_date":"2017-11-06T00:00:00.000Z","publication_date":"2019-12-31T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":28,"abstract":"An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Systems and method for mapping FIFOs to processor address space","description":"An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with me","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10521390","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10521390","citation_suggestion":"Patentable. \"Systems and method for mapping FIFOs to processor address space\" (US-10521390). https://patentable.app/patents/US-10521390","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10521390","json":"https://patentable.app/api/llm-context/US-10521390","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T12:44:44.243Z"}