{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10522237","patent":{"patent_number":"US-10522237","title":"Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation","assignee":null,"inventors":[],"filing_date":"2016-10-07T00:00:00.000Z","publication_date":"2019-12-31T00:00:00.000Z","cpc_codes":["G11C","G06F","G06F","G06F","G06F","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G06F","G06F","G11C","G11C","G11C","G11C"],"num_claims":16,"abstract":"Low power very large scale integrated (VLSI) designs using a circuit failure in sequential cells as low voltage check for limit of operation of a design are provided. One such method involves the adding a plurality of bits for sequential elements in the design including sets of flip-flops, RAMs, ROMs and register files to add parity or single error correct and double error detect mechanism, a method to detect the parity errors or a single bit error and a double bit error in the sequential elements, starting at a voltage of operation at a nominal value and gradually lowering voltage setting till a first error is detected in the sequential elements, increasing the voltage of operation by predetermined step above a voltage of first fail to achieve an optimal voltage setting of a correct operation of the design, storing this optimal voltage setting in anon-volatile memory for a subsequent use."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation","description":"Low power very large scale integrated (VLSI) designs using a circuit failure in sequential cells as low voltage check for limit of operation of a design are provided. One such method involves the addi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10522237","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10522237","citation_suggestion":"Patentable. \"Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation\" (US-10522237). https://patentable.app/patents/US-10522237","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10522237","json":"https://patentable.app/api/llm-context/US-10522237","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T21:21:16.838Z"}