{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10522648","patent":{"patent_number":"US-10522648","title":"Method for manufacturing electronic component for heterojunction provided with buried barrier layer","assignee":null,"inventors":[],"filing_date":"2018-10-03T00:00:00.000Z","publication_date":"2019-12-31T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":8,"abstract":"The invention relates to a process for manufacturing a heterojunction electronic component provided with an embedded barrier layer, the process comprising: depositing by epitaxy, in a vapour phase epitaxial growth chamber with an atmosphere exhibiting a first nonzero ammonia concentration, of a GaN precursor layer of the embedded barrier layer, comprising a first layer doped with a Mg or Fe dopant; placing, while maintaining the substrate in the chamber, the atmosphere at a second ammonia concentration at most equal to a third of the first concentration, in order to remove an upper part of the precursor layer; and then after the removal of the said upper part, while maintaining the substrate in the chamber, depositing by epitaxy of a layer of semiconductor material of the heterojunction electronic component to be manufactured, the said precursor layer then forming the embedded barrier layer under the said layer of semiconductor material."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for manufacturing electronic component for heterojunction provided with buried barrier layer","description":"The invention relates to a process for manufacturing a heterojunction electronic component provided with an embedded barrier layer, the process comprising: depositing by epitaxy, in a vapour phase epi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10522648","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10522648","citation_suggestion":"Patentable. \"Method for manufacturing electronic component for heterojunction provided with buried barrier layer\" (US-10522648). https://patentable.app/patents/US-10522648","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10522648","json":"https://patentable.app/api/llm-context/US-10522648","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T11:13:08.409Z"}