{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10522663","patent":{"patent_number":"US-10522663","title":"Integrated JFET structure with implanted backgate","assignee":null,"inventors":[],"filing_date":"2018-08-20T00:00:00.000Z","publication_date":"2019-12-31T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L"],"num_claims":20,"abstract":"A method of forming an electronic device includes forming first, second and third doped regions at a surface of a semiconductor substrate. A first buried layer is located within the semiconductor substrate below the first, second and third doped regions. Fourth and fifth doped regions are laterally spaced apart along the substrate and extend from the surface of the substrate to the first buried layer, the first, second and third doped regions being located between the fourth and fifth doped regions. A second buried layer is formed within the substrate and between the fourth and fifth doped regions such that a first portion of the semiconductor substrate is located between the first buried layer and the second buried layer, and a second portion of the semiconductor substrate is located between the first, second and third doped regions and the second buried layer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Integrated JFET structure with implanted backgate","description":"A method of forming an electronic device includes forming first, second and third doped regions at a surface of a semiconductor substrate. A first buried layer is located within the semiconductor subs","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10522663","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10522663","citation_suggestion":"Patentable. \"Integrated JFET structure with implanted backgate\" (US-10522663). https://patentable.app/patents/US-10522663","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10522663","json":"https://patentable.app/api/llm-context/US-10522663","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T18:02:02.098Z"}