{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10522949","patent":{"patent_number":"US-10522949","title":"Optimized pin pattern for high speed input/output","assignee":null,"inventors":[],"filing_date":"2018-08-08T00:00:00.000Z","publication_date":"2019-12-31T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":20,"abstract":"Pin layouts for HSIO require a large number of pins due to isolation requirements. Differential signaling can be used in high speed transmission and reception. A single lane for operation at 6 to 8 Gbps speed typically a total of six to eight pins. At higher speeds, conventional technique to meet isolation requirements is to increase the number of ground pins per lane. With many lanes, the number of pins can become cumbersome. To address such issues, it is proposed to provide pin patterns that leverage differential cancellation to enhance signal isolation so that operation speed can increase while also reducing the number of pins so that the number of pins of a package is less cumbersome."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Optimized pin pattern for high speed input/output","description":"Pin layouts for HSIO require a large number of pins due to isolation requirements. Differential signaling can be used in high speed transmission and reception. A single lane for operation at 6 to 8 Gb","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10522949","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10522949","citation_suggestion":"Patentable. \"Optimized pin pattern for high speed input/output\" (US-10522949). https://patentable.app/patents/US-10522949","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10522949","json":"https://patentable.app/api/llm-context/US-10522949","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T13:45:30.512Z"}