{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10529421","patent":{"patent_number":"US-10529421","title":"Memory system having resistive memory device for scheduling write command and operating method thereof","assignee":null,"inventors":[],"filing_date":"2018-06-13T00:00:00.000Z","publication_date":"2020-01-07T00:00:00.000Z","cpc_codes":["G11C","G06F","G06F","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":24,"abstract":"A memory system includes a memory cell array including a plurality of resistive memory cells; a peripheral circuit suitable for providing a set pulse or a reset pulse with write data into a selected memory cell among the resistive memory cells, based on a write command; and a memory controller suitable for providing the write command with the write data to the peripheral circuit and scheduling the write command based on an amount of power consumption calculated depending on the number of either low bits or high bits in the write data."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory system having resistive memory device for scheduling write command and operating method thereof","description":"A memory system includes a memory cell array including a plurality of resistive memory cells; a peripheral circuit suitable for providing a set pulse or a reset pulse with write data into a selected m","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10529421","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10529421","citation_suggestion":"Patentable. \"Memory system having resistive memory device for scheduling write command and operating method thereof\" (US-10529421). https://patentable.app/patents/US-10529421","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10529421","json":"https://patentable.app/api/llm-context/US-10529421","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T08:44:14.058Z"}