{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10529844","patent":{"patent_number":"US-10529844","title":"Structure of trench-vertical double diffused MOS transistor and method of forming the same","assignee":null,"inventors":[],"filing_date":"2016-07-18T00:00:00.000Z","publication_date":"2020-01-07T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":2,"abstract":"A structure of trench VDMOS transistor comprises an n− epi-layer/ n+ substrate having trench gates formed therein, which have a trench oxide layer conformally formed and filled with a first poly-Si layer. A plurality of MOS structure formed on the mesas. Doubled diffused source regions are formed asides the MOS structure. An inter-metal dielectric layer is formed on the resulted surfaces. An interconnecting metal layer patterned as two is formed on inter-metal dielectric layer. The one is for source regions and the first poly-Si layer connection by source contact plugs and the other for the gate connection by gate contact plugs. In the other embodiment, the trenches are filled with a stack layer of a first oxide layer/a first poly-Si layer. The MOS gates with their second poly-Si layer in a form of rows are formed on the first oxide layer and the mesas. An inter-metal dielectric layer is formed on the resulted surfaces. An interconnecting metal layer is formed on the inter-metal dielectric layer and through the source contact plugs connecting the source regions and the first poly-Si layer. The drain electrode is formed on the rear surface of the n+ substrate for both embodiments."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Structure of trench-vertical double diffused MOS transistor and method of forming the same","description":"A structure of trench VDMOS transistor comprises an n− epi-layer/ n+ substrate having trench gates formed therein, which have a trench oxide layer conformally formed and filled with a first poly-Si la","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10529844","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10529844","citation_suggestion":"Patentable. \"Structure of trench-vertical double diffused MOS transistor and method of forming the same\" (US-10529844). https://patentable.app/patents/US-10529844","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10529844","json":"https://patentable.app/api/llm-context/US-10529844","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T10:09:03.091Z"}