{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10531030","patent":{"patent_number":"US-10531030","title":"Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register","assignee":null,"inventors":[],"filing_date":"2019-06-21T00:00:00.000Z","publication_date":"2020-01-07T00:00:00.000Z","cpc_codes":["H04N","G06F","G06F","G06F","G06T"],"num_claims":20,"abstract":"A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register","description":"A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10531030","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10531030","citation_suggestion":"Patentable. \"Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register\" (US-10531030). https://patentable.app/patents/US-10531030","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10531030","json":"https://patentable.app/api/llm-context/US-10531030","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T01:15:46.355Z"}