{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10534396","patent":{"patent_number":"US-10534396","title":"Method, and a synchronous digital circuit, for preventing propagation of set-up timing data errors","assignee":null,"inventors":[],"filing_date":"2018-03-05T00:00:00.000Z","publication_date":"2020-01-14T00:00:00.000Z","cpc_codes":["G06F","G06F","H04L"],"num_claims":15,"abstract":"There is disclosed a synchronous digital circuit having a system clock and for processing a data signal, wherein the digital circuit comprises a data path, a hard macro having a macro input, a logic circuit in the data path upstream of the macro input and having a first part and a second part, the second part being immediately upstream of the macro input, a set-up timing error detector having an input, wherein the input is on the data path between the first part and the second part, and a timing correction unit, wherein the data transit time across the second part is equal to or less than one half of a clock period, and wherein the timing correction unit is configured to correct, in response to the set-up timing error detector detecting a set-up timing error, the detected set-up timing error before the data reaches the macro input."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method, and a synchronous digital circuit, for preventing propagation of set-up timing data errors","description":"There is disclosed a synchronous digital circuit having a system clock and for processing a data signal, wherein the digital circuit comprises a data path, a hard macro having a macro input, a logic c","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10534396","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10534396","citation_suggestion":"Patentable. \"Method, and a synchronous digital circuit, for preventing propagation of set-up timing data errors\" (US-10534396). https://patentable.app/patents/US-10534396","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10534396","json":"https://patentable.app/api/llm-context/US-10534396","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T08:35:10.672Z"}