{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10534545","patent":{"patent_number":"US-10534545","title":"Three-dimensional stacked memory optimizations for latency and power","assignee":null,"inventors":[],"filing_date":"2017-12-20T00:00:00.000Z","publication_date":"2020-01-14T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G11C","G11C","G11C","G11C","G11C","G06F","G06F","G06F","G11C"],"num_claims":20,"abstract":"An aspect includes receiving a request to write data to a memory that includes a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). The write request is received by a hypervisor from an application executing on a virtual machine managed by the hypervisor. In response to receiving the request a latency requirement of accesses to the write data is determined. A physical location on a memory device in the stack of memory devices is assigned to the write data based at least in part on the latency requirement and a position of the memory device in the stack of memory devices. A write command that includes the physical location and the write data is sent to a memory controller."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Three-dimensional stacked memory optimizations for latency and power","description":"An aspect includes receiving a request to write data to a memory that includes a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10534545","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10534545","citation_suggestion":"Patentable. \"Three-dimensional stacked memory optimizations for latency and power\" (US-10534545). https://patentable.app/patents/US-10534545","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10534545","json":"https://patentable.app/api/llm-context/US-10534545","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T22:37:06.535Z"}