{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10534731","patent":{"patent_number":"US-10534731","title":"Interface for memory having a cache and multiple independent arrays","assignee":null,"inventors":[],"filing_date":"2018-03-19T00:00:00.000Z","publication_date":"2020-01-14T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G11C","G11C","G11C","G11C","G06F","G06F","G06F","G06F","G06F","G11C"],"num_claims":33,"abstract":"The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Interface for memory having a cache and multiple independent arrays","description":"The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays,","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10534731","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10534731","citation_suggestion":"Patentable. \"Interface for memory having a cache and multiple independent arrays\" (US-10534731). https://patentable.app/patents/US-10534731","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10534731","json":"https://patentable.app/api/llm-context/US-10534731","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T06:39:39.941Z"}