{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10535402","patent":{"patent_number":"US-10535402","title":"Resistance variable memory apparatus","assignee":null,"inventors":[],"filing_date":"2017-08-18T00:00:00.000Z","publication_date":"2020-01-14T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":16,"abstract":"A resistance variable memory apparatus includes a memory cell array region and a peripheral region disposed along an edge of the memory cell region. The memory cell array region may have a plurality of memory banks each of which includes at least one memory block. The resistance variable memory apparatus may include a data transmission block transmitting data between the plurality of memory banks and the peripheral region. The data transmission block includes a plurality of lower global input/output lines shared by pairs of adjacent memory banks, a plurality of lower multiplexers receiving data from pairs of adjacent lower global input/output lines and outputting data inputted from one of the lower global input/output lines, and an upper multiplexer receiving data output from the plurality of lower multiplexers and outputting data input from one of the lower multiplexers."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Resistance variable memory apparatus","description":"A resistance variable memory apparatus includes a memory cell array region and a peripheral region disposed along an edge of the memory cell region. The memory cell array region may have a plurality o","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10535402","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10535402","citation_suggestion":"Patentable. \"Resistance variable memory apparatus\" (US-10535402). https://patentable.app/patents/US-10535402","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10535402","json":"https://patentable.app/api/llm-context/US-10535402","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T03:35:44.296Z"}