{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10535667","patent":{"patent_number":"US-10535667","title":"Memory array and semiconductor chip","assignee":null,"inventors":[],"filing_date":"2018-09-10T00:00:00.000Z","publication_date":"2020-01-14T00:00:00.000Z","cpc_codes":["G11C"],"num_claims":20,"abstract":"A memory array and a semiconductor chip are provided. The memory array includes memory cells, each includes: first and second pull-up transistors, first and second pull-down transistors, and first and second pass-gate transistors. A source/drain of the first pull-up transistor is coupled to a source/drain of the first pull-down transistor. A source/drain of the second pull-up transistor is coupled to a source/drain of the second pull-down transistor. Gates of the second pull-up and pull-down transistors are coupled to the first node. Gates of the first pull-up and pull-down transistors are coupled to the second node. The first and second pass-gate transistors are respectively coupled to the first and second nodes. The first and second pull-up transistors respectively include a first active structure having a bottom portion including a strained semiconductor material and a top portion including an unstrained semiconductor material. The first active structures continuously extend across the memory array."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory array and semiconductor chip","description":"A memory array and a semiconductor chip are provided. The memory array includes memory cells, each includes: first and second pull-up transistors, first and second pull-down transistors, and first and","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10535667","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10535667","citation_suggestion":"Patentable. \"Memory array and semiconductor chip\" (US-10535667). https://patentable.app/patents/US-10535667","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10535667","json":"https://patentable.app/api/llm-context/US-10535667","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T14:07:19.004Z"}