{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10535695","patent":{"patent_number":"US-10535695","title":"Stacked wafer arrangement for global shutter pixels utilizing capacitive deep trench isolations","assignee":null,"inventors":[],"filing_date":"2018-03-13T00:00:00.000Z","publication_date":"2020-01-14T00:00:00.000Z","cpc_codes":["H04N","H04N","H04N","H04N","H04N","H04N"],"num_claims":25,"abstract":"Described herein is an electronic device that includes a first integrated circuit die having formed therein at least one photodiode and readout circuitry to convert charge generated by the at least one photodiode to a read voltage and to selectively output the read voltage. A second integrated circuit die is in a stacked arrangement with the first integrated circuit die and has formed therein storage circuitry to selectively transfer the read voltage to at least one storage capacitor for storage as a stored voltage and to selectively transfer the stored voltage to an output. The at least one storage capacitor is formed from a capacitive deep trench isolation. There is an interconnect between the first and second integrated circuit dies for coupling the readout circuitry to the storage circuitry."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Stacked wafer arrangement for global shutter pixels utilizing capacitive deep trench isolations","description":"Described herein is an electronic device that includes a first integrated circuit die having formed therein at least one photodiode and readout circuitry to convert charge generated by the at least on","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10535695","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10535695","citation_suggestion":"Patentable. \"Stacked wafer arrangement for global shutter pixels utilizing capacitive deep trench isolations\" (US-10535695). https://patentable.app/patents/US-10535695","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10535695","json":"https://patentable.app/api/llm-context/US-10535695","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T22:37:23.173Z"}