{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10535750","patent":{"patent_number":"US-10535750","title":"Semiconductor device manufacturing method with reduced gate electrode height loss and related devices","assignee":null,"inventors":[],"filing_date":"2017-11-28T00:00:00.000Z","publication_date":"2020-01-14T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L"],"num_claims":20,"abstract":"A semiconductor device and its manufacturing method are presented. The manufacturing method includes providing a semiconductor structure comprising a substrate, at least one source region on the substrate, an interlayer dielectric layer covering a portion of the source region and having a cavity on the source region, and a pseudo gate insulation layer at the bottom of the cavity covering a portion of the source region; forming a barrier layer in the cavity; forming a loss reduction region in the interlayer dielectric layer by conducting an ion implantation process comprising silicon ion or carbon ion; removing the barrier layer; removing the pseudo gate insulation layer to expose a portion of the source region; and forming a gate structure on the exposed portion of the source region. This inventive concept reduces the loss of the interlayer dielectric layer, thus reduces the height loss of the gate electrode."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor device manufacturing method with reduced gate electrode height loss and related devices","description":"A semiconductor device and its manufacturing method are presented. The manufacturing method includes providing a semiconductor structure comprising a substrate, at least one source region on the subst","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10535750","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10535750","citation_suggestion":"Patentable. \"Semiconductor device manufacturing method with reduced gate electrode height loss and related devices\" (US-10535750). https://patentable.app/patents/US-10535750","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10535750","json":"https://patentable.app/api/llm-context/US-10535750","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T17:05:48.297Z"}