{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10540170","patent":{"patent_number":"US-10540170","title":"Concurrent I/O enclosure firmware/field-programmable gate array (FPGA) update in a multi-node environment","assignee":null,"inventors":[],"filing_date":"2018-09-12T00:00:00.000Z","publication_date":"2020-01-21T00:00:00.000Z","cpc_codes":["G06F","H04L","H04L"],"num_claims":15,"abstract":"Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Concurrent I/O enclosure firmware/field-programmable gate array (FPGA) update in a multi-node environment","description":"Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10540170","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10540170","citation_suggestion":"Patentable. \"Concurrent I/O enclosure firmware/field-programmable gate array (FPGA) update in a multi-node environment\" (US-10540170). https://patentable.app/patents/US-10540170","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10540170","json":"https://patentable.app/api/llm-context/US-10540170","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T16:25:37.618Z"}