{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10540467","patent":{"patent_number":"US-10540467","title":"System, method, and computer program product for handling combinational loops associated with the formal verification of an electronic circuit design","assignee":null,"inventors":[],"filing_date":"2018-04-03T00:00:00.000Z","publication_date":"2020-01-21T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":20,"abstract":"The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and identifying at least one combinational loop associated with the electronic circuit design. Embodiments may also include extracting, for each component of the loop, a set of logic conditions and modeling the at least one combinational loop. Embodiments may further include providing a graphical user interface configured to display one or more constraint candidates and determining whether or not a conflict exists between constraint candidates. Embodiments may also include ranking the constraint candidates, based upon, at least in part, a number of loops disabled and one or more disabled loop characteristics."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"System, method, and computer program product for handling combinational loops associated with the formal verification of an electronic circuit design","description":"The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and identifying at least one combinational ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10540467","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10540467","citation_suggestion":"Patentable. \"System, method, and computer program product for handling combinational loops associated with the formal verification of an electronic circuit design\" (US-10540467). https://patentable.app/patents/US-10540467","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10540467","json":"https://patentable.app/api/llm-context/US-10540467","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T23:28:50.044Z"}