{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10540469","patent":{"patent_number":"US-10540469","title":"Verifying sequential equivalence for randomly initialized designs","assignee":null,"inventors":[],"filing_date":"2017-12-18T00:00:00.000Z","publication_date":"2020-01-21T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":19,"abstract":"A computerized method for mapping of electronic designs comprising using at least one hardware processor for receiving a first hardware design model and a second hardware design model, each hardware design model configured to receive a startup state and send digital output values. Hardware processor(s) are used for generating a plurality of initial states. Hardware processor(s) are used for computing, using each one of the first and second hardware design models, at least one specific output value for each one of the plurality of initial states. Hardware processor(s) are used for selecting corresponding initial states that produce equivalent at least one specific output value between the first hardware design model and the second hardware design model. Hardware processor(s) are used for storing the selected corresponding initial states as mappings between the first hardware design model and the second hardware design model."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Verifying sequential equivalence for randomly initialized designs","description":"A computerized method for mapping of electronic designs comprising using at least one hardware processor for receiving a first hardware design model and a second hardware design model, each hardware d","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10540469","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10540469","citation_suggestion":"Patentable. \"Verifying sequential equivalence for randomly initialized designs\" (US-10540469). https://patentable.app/patents/US-10540469","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10540469","json":"https://patentable.app/api/llm-context/US-10540469","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T11:52:40.116Z"}