{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10541020","patent":{"patent_number":"US-10541020","title":"Controller architecture for reducing on-die capacitance","assignee":null,"inventors":[],"filing_date":"2018-02-27T00:00:00.000Z","publication_date":"2020-01-21T00:00:00.000Z","cpc_codes":["G11C","G06F","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":12,"abstract":"The disclosed controller includes a DDR architecture that includes a dual-channel interface designed to include DQS IO ports configured to generate a first DQS signal that is a distance of substantially 0.125 times the period of a clock signal (ΔT denoting the 0.125 of the period of the clock signal) ahead of a rising edge of the clock signal and a second DQS signal that is a distance of substantially 0.125 times the period of the clock signal behind the rising edge of a clock signal. If ΔT is more than a tDQSS then ΔT is set to tDQSS, where tDQSS is a maximum allowable time between either DQS signal and the rising edge of the clock signal."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Controller architecture for reducing on-die capacitance","description":"The disclosed controller includes a DDR architecture that includes a dual-channel interface designed to include DQS IO ports configured to generate a first DQS signal that is a distance of substantial","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10541020","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10541020","citation_suggestion":"Patentable. \"Controller architecture for reducing on-die capacitance\" (US-10541020). https://patentable.app/patents/US-10541020","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10541020","json":"https://patentable.app/api/llm-context/US-10541020","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T02:44:52.523Z"}