{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10541220","patent":{"patent_number":"US-10541220","title":"Printed repassivation for wafer chip scale packaging","assignee":null,"inventors":[],"filing_date":"2018-08-02T00:00:00.000Z","publication_date":"2020-01-21T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":26,"abstract":"Described examples provide integrated circuits and methods, including forming a conductive seed layer at least partially above a conductive feature of a wafer, forming a conductive structure on at least a portion of the conductive seed layer, performing a printing process that forms a polymer material on a side of the wafer proximate a side of the conductive structure, curing the deposited polymer material, and attaching a solder ball structure to a side of the conductive structure."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Printed repassivation for wafer chip scale packaging","description":"Described examples provide integrated circuits and methods, including forming a conductive seed layer at least partially above a conductive feature of a wafer, forming a conductive structure on at lea","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10541220","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10541220","citation_suggestion":"Patentable. \"Printed repassivation for wafer chip scale packaging\" (US-10541220). https://patentable.app/patents/US-10541220","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10541220","json":"https://patentable.app/api/llm-context/US-10541220","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T13:28:33.110Z"}