{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10546081","patent":{"patent_number":"US-10546081","title":"Full memory logical erase for circuit verification","assignee":null,"inventors":[],"filing_date":"2018-09-18T00:00:00.000Z","publication_date":"2020-01-28T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G11C","G11C","G11C","G11C"],"num_claims":12,"abstract":"A hardware model of a memory comprises: first circuitry configured to supply a memory status value for the memory which is changed upon a full-memory erase operation; second circuitry configured to supply a sector status value for each memory sector of the memory which is changed to a value equal to the memory status value when a write operation is performed on the each memory sector of the memory; and third circuitry configured to supply, when a read operation is performed on a memory sector of the memory, a value stored in the memory sector as output of the read operation if the sector status value for the memory sector is equal to the memory status value or a predefined value as the output of the read operation in other situations."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Full memory logical erase for circuit verification","description":"A hardware model of a memory comprises: first circuitry configured to supply a memory status value for the memory which is changed upon a full-memory erase operation; second circuitry configured to su","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10546081","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10546081","citation_suggestion":"Patentable. \"Full memory logical erase for circuit verification\" (US-10546081). https://patentable.app/patents/US-10546081","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10546081","json":"https://patentable.app/api/llm-context/US-10546081","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T08:55:34.417Z"}