{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10546082","patent":{"patent_number":"US-10546082","title":"Resistor network reduction for full-chip simulation of current density","assignee":null,"inventors":[],"filing_date":"2018-01-17T00:00:00.000Z","publication_date":"2020-01-28T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F"],"num_claims":15,"abstract":"Aspects of technology disclosed herein relate to techniques of a full-circuit simulation-based circuit design verification. A simulation is performed to determine current data of parasitic resistors in one or more parasitic resistance networks in power supply circuitry of a circuit design by injecting a current into each one of the one or more parasitic resistance networks. Based on the current data, non-current carrying parasitic resistors are removed from the one or more parasitic resistance network to generate one or more reduced parasitic resistance network. Using the one or more reduced parasitic resistance networks, a full-circuit simulation is performed to obtain current density information. A circuit design verification of the circuit design is then performed based on the current density information."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Resistor network reduction for full-chip simulation of current density","description":"Aspects of technology disclosed herein relate to techniques of a full-circuit simulation-based circuit design verification. A simulation is performed to determine current data of parasitic resistors i","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10546082","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10546082","citation_suggestion":"Patentable. \"Resistor network reduction for full-chip simulation of current density\" (US-10546082). https://patentable.app/patents/US-10546082","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10546082","json":"https://patentable.app/api/llm-context/US-10546082","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T01:19:45.889Z"}