{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10546742","patent":{"patent_number":"US-10546742","title":"Method to reduce trap-induced capacitance in interconnect dielectric barrier stack","assignee":null,"inventors":[],"filing_date":"2018-12-31T00:00:00.000Z","publication_date":"2020-01-28T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":19,"abstract":"The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method to reduce trap-induced capacitance in interconnect dielectric barrier stack","description":"The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrat","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10546742","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10546742","citation_suggestion":"Patentable. \"Method to reduce trap-induced capacitance in interconnect dielectric barrier stack\" (US-10546742). https://patentable.app/patents/US-10546742","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10546742","json":"https://patentable.app/api/llm-context/US-10546742","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T22:15:02.877Z"}