{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11233034","patent":{"patent_number":"US-11233034","title":"Stacked memory routing techniques","assignee":null,"inventors":[],"filing_date":"2019-09-19T00:00:00.000Z","publication_date":"2022-01-25T00:00:00.000Z","cpc_codes":["H01L","G11C","G11C","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","G11C","G11C","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":13,"abstract":"Techniques for signal routing between a host and dynamic random-access memory (DRAM) are provided. In an example, a routing layer for a dynamic random-access memory die (DRAM can include multiple through silicon via (TSV) terminations configured to electrically couple with TSVs of the DRAM, an intermediate interface area, and multiple routing traces. the multiple TSV terminations can be arranged in multiple TSV areas. The multiple TSV areas can be arranged in two columns. The intermediate interface area can include multiple micro-pillar bump terminations configured to couple, via a micro-pillar bump, with corresponding micro-pillar bump terminations of a semiconductor interposer. The multiple routing traces can couple control TSV terminations of the multiple TSV areas with a corresponding micro-pillar bump termination of the intermediate interface."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Stacked memory routing techniques","description":"Techniques for signal routing between a host and dynamic random-access memory (DRAM) are provided. In an example, a routing layer for a dynamic random-access memory die (DRAM can include multiple thro","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11233034","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11233034","citation_suggestion":"Patentable. \"Stacked memory routing techniques\" (US-11233034). https://patentable.app/patents/US-11233034","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11233034","json":"https://patentable.app/api/llm-context/US-11233034","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T07:00:02.341Z"}