{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11233040","patent":{"patent_number":"US-11233040","title":"Integration of high density cross-point memory and CMOS logic for high density low latency eNVM and eDRAM applications","assignee":null,"inventors":[],"filing_date":"2017-09-25T00:00:00.000Z","publication_date":"2022-01-25T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":25,"abstract":"An embedded cross-point memory array is described. In an example, an integrated circuit structure includes a first die including a cross-point memory array comprising separate memory blocks, the memory blocks including orthogonally arranged conductive lines, and memory elements at cross-sections of the conductive lines. A first plurality of sockets is on the first die adjacent to the memory blocks, the first plurality of sockets comprising a first plurality of pads that connect to at least a portion to the conductive lines of the corresponding memory block. A second die includes logic circuitry and a second plurality of sockets comprising a second plurality of pads at least partially aligned with positions of the first plurality of pads on the first die. A top of the first die and a top of the second die face one another, wherein the first plurality of pads are bonded with the second plurality pads to directly connect the cross-point memory array to the logic circuitry."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Integration of high density cross-point memory and CMOS logic for high density low latency eNVM and eDRAM applications","description":"An embedded cross-point memory array is described. In an example, an integrated circuit structure includes a first die including a cross-point memory array comprising separate memory blocks, the memor","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11233040","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11233040","citation_suggestion":"Patentable. \"Integration of high density cross-point memory and CMOS logic for high density low latency eNVM and eDRAM applications\" (US-11233040). https://patentable.app/patents/US-11233040","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11233040","json":"https://patentable.app/api/llm-context/US-11233040","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T05:56:01.647Z"}