{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11233512","patent":{"patent_number":"US-11233512","title":"Buffer circuit, receiver circuit including the buffer circuit, and semiconductor apparatus including the receiver circuit","assignee":null,"inventors":[],"filing_date":"2020-09-10T00:00:00.000Z","publication_date":"2022-01-25T00:00:00.000Z","cpc_codes":["G11C","G11C"],"num_claims":20,"abstract":"The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Buffer circuit, receiver circuit including the buffer circuit, and semiconductor apparatus including the receiver circuit","description":"The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a s","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11233512","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11233512","citation_suggestion":"Patentable. \"Buffer circuit, receiver circuit including the buffer circuit, and semiconductor apparatus including the receiver circuit\" (US-11233512). https://patentable.app/patents/US-11233512","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11233512","json":"https://patentable.app/api/llm-context/US-11233512","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T23:56:34.333Z"}