{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11238202","patent":{"patent_number":"US-11238202","title":"Verifying glitches in reset path using formal verification and simulation","assignee":null,"inventors":[],"filing_date":"2020-06-24T00:00:00.000Z","publication_date":"2022-02-01T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":19,"abstract":"A method and a system for identifying glitches in a circuit are provided. The method includes identifying a sub-circuit that drives a net from a plurality of nets in a circuit, generating a glitch detection circuit comprising dual-rail encoding from the net to a signal driver of the sub-circuit, modifying the sub-circuit to include the glitch detection circuit, generating an optimized hardware design language (HDL) output file associated with the glitch detection circuit and the sub-circuit, and performing a simulation or a formal verification of the optimized HDL output file to determine whether a signal associated with the net glitches."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Verifying glitches in reset path using formal verification and simulation","description":"A method and a system for identifying glitches in a circuit are provided. The method includes identifying a sub-circuit that drives a net from a plurality of nets in a circuit, generating a glitch det","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11238202","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11238202","citation_suggestion":"Patentable. \"Verifying glitches in reset path using formal verification and simulation\" (US-11238202). https://patentable.app/patents/US-11238202","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11238202","json":"https://patentable.app/api/llm-context/US-11238202","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T14:59:42.022Z"}