{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11239072","patent":{"patent_number":"US-11239072","title":"Cut metal gate process for reducing transistor spacing","assignee":null,"inventors":[],"filing_date":"2020-04-21T00:00:00.000Z","publication_date":"2022-02-01T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A semiconductor structure includes a substrate, a pair of first fins extending from the substrate, a pair of second fins extending from the substrate, an isolation feature over the substrate and separating bottom portions of the first and the second fins, a pair of first epitaxial semiconductor features over the pair of first fins respectively, a pair of second epitaxial semiconductor features over the pair of second fins respectively, and a first dielectric feature sandwiched between and separating the pair of first epitaxial semiconductor features. The pair of second epitaxial semiconductor features merge with each other."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Cut metal gate process for reducing transistor spacing","description":"A semiconductor structure includes a substrate, a pair of first fins extending from the substrate, a pair of second fins extending from the substrate, an isolation feature over the substrate and separ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11239072","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11239072","citation_suggestion":"Patentable. \"Cut metal gate process for reducing transistor spacing\" (US-11239072). https://patentable.app/patents/US-11239072","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11239072","json":"https://patentable.app/api/llm-context/US-11239072","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T00:14:41.604Z"}