{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11239960","patent":{"patent_number":"US-11239960","title":"Characterization of in-chip error correction circuits and related semiconductor memory devices/memory systems","assignee":null,"inventors":[],"filing_date":"2020-10-26T00:00:00.000Z","publication_date":"2022-02-01T00:00:00.000Z","cpc_codes":["H04L","G06F","G11C","G11C"],"num_claims":8,"abstract":"A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Characterization of in-chip error correction circuits and related semiconductor memory devices/memory systems","description":"A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11239960","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11239960","citation_suggestion":"Patentable. \"Characterization of in-chip error correction circuits and related semiconductor memory devices/memory systems\" (US-11239960). https://patentable.app/patents/US-11239960","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11239960","json":"https://patentable.app/api/llm-context/US-11239960","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T23:46:35.778Z"}