{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11243245","patent":{"patent_number":"US-11243245","title":"Analysis method for semiconductor device","assignee":null,"inventors":[],"filing_date":"2020-03-25T00:00:00.000Z","publication_date":"2022-02-08T00:00:00.000Z","cpc_codes":["G06F","H01L","H01L","H01L"],"num_claims":12,"abstract":"The present disclosure provides an analysis method of a semiconductor device, and the semiconductor device comprises a plurality of HKMG fin field effect transistors and a wafer on which the plurality of HKMG fin field effect transistors are located, and the analysis method comprises: performing acceptance testing on the wafer to be tested; constructing an N-type model based on the position of each N-type transistor at the surface of the wafer to be tested and the corresponding acceptance test result, constructing a P-type model based on the position of each P-type transistor at the surface of the wafer to be tested and the corresponding acceptance test result, and constructing an N/P ratio model corresponding to the surface of the wafer to be tested based on the N-type model and the P-type model; and identifying the N/P ratio model based on a preset standard wafer model to determine whether the wafer to be tested is compliant based on the N/P ratio model. According to the analysis method provided by the present disclosure, it is possible to find a non-compliant wafer among a plurality of wafers, thereby enabling the subsequent targeted parameter analysis and improving the efficiency of optimizing the process scheme."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Analysis method for semiconductor device","description":"The present disclosure provides an analysis method of a semiconductor device, and the semiconductor device comprises a plurality of HKMG fin field effect transistors and a wafer on which the plurality","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11243245","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11243245","citation_suggestion":"Patentable. \"Analysis method for semiconductor device\" (US-11243245). https://patentable.app/patents/US-11243245","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11243245","json":"https://patentable.app/api/llm-context/US-11243245","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T08:28:54.418Z"}