{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11244713","patent":{"patent_number":"US-11244713","title":"Variable page size architecture","assignee":null,"inventors":[],"filing_date":"2020-01-21T00:00:00.000Z","publication_date":"2022-02-08T00:00:00.000Z","cpc_codes":["G11C","G11C","G06F","G11C","G11C","G11C","G11C","G11C"],"num_claims":19,"abstract":"Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Variable page size architecture","description":"Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in pa","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11244713","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11244713","citation_suggestion":"Patentable. \"Variable page size architecture\" (US-11244713). https://patentable.app/patents/US-11244713","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11244713","json":"https://patentable.app/api/llm-context/US-11244713","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T11:37:23.861Z"}