{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11244949","patent":{"patent_number":"US-11244949","title":"Semiconductor device having stacked transistor pairs and method of forming same","assignee":null,"inventors":[],"filing_date":"2019-06-14T00:00:00.000Z","publication_date":"2022-02-08T00:00:00.000Z","cpc_codes":["B82Y","G11C","G11C","G11C"],"num_claims":15,"abstract":"The disclosed technology generally relates to semiconductor devices and more particularly to a semiconductor device comprising stacked complementary transistor pairs. In one aspect, a semiconductor device comprises first and second sets of transistors comprising a pass transistor and a stacked complementary transistor pair of a lower transistor and an upper transistor, wherein first transistor comprises a semiconductor channel extending along a horizontal first fin track, and each second transistor comprises a semiconductor channel extending along a second fin track parallel to the first fin track, and wherein the semiconductor channels of the pass transistors and of the lower transistors are arranged at a first level and the semiconductor channels of said upper transistors are arranged at a second level, a first tall gate electrode forming a common gate for the first complementary transistor pair and arranged along a horizontal first gate track, and a first short gate electrode forming a gate for the first pass transistor and arranged along a second gate track, a second tall gate electrode forming a common gate for the second complementary transistor pair and arranged along the second gate track, a second short gate electrode forming a gate for the second pass transistor and arranged along the first gate track, first and second contact arrangements forming a common drain contact for the transistors of the first set and the second set, respectively, and first and second cross-couple contacts extending horizontally between and interconnecting the first tall gate electrode and the second contact arrangement, and the second tall gate electrode and the first contact arrangement, respectively."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor device having stacked transistor pairs and method of forming same","description":"The disclosed technology generally relates to semiconductor devices and more particularly to a semiconductor device comprising stacked complementary transistor pairs. In one aspect, a semiconductor de","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11244949","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11244949","citation_suggestion":"Patentable. \"Semiconductor device having stacked transistor pairs and method of forming same\" (US-11244949). https://patentable.app/patents/US-11244949","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11244949","json":"https://patentable.app/api/llm-context/US-11244949","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T21:55:22.246Z"}