{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11249905","patent":{"patent_number":"US-11249905","title":"Techniques for configuring a processor to function as multiple, separate processors","assignee":null,"inventors":[],"filing_date":"2019-09-05T00:00:00.000Z","publication_date":"2022-02-15T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Techniques for configuring a processor to function as multiple, separate processors","description":"A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computatio","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11249905","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11249905","citation_suggestion":"Patentable. \"Techniques for configuring a processor to function as multiple, separate processors\" (US-11249905). https://patentable.app/patents/US-11249905","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11249905","json":"https://patentable.app/api/llm-context/US-11249905","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T15:36:00.814Z"}