{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11250196","patent":{"patent_number":"US-11250196","title":"Conductor subdivision in physical integrated circuit layout for parasitic extraction","assignee":null,"inventors":[],"filing_date":"2018-08-31T00:00:00.000Z","publication_date":"2022-02-15T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"A computing system can perform a layout-to-schematic process on a geometric layout design of an integrated circuit, which can generate a device-level layout design for the integrated circuit. The computing system also can perform a parasitic extraction process on the geometric layout design by utilizing the device-level layout design for the integrated circuit. The computing system implementing the parasitic extraction process can sub-divide a conductor in the device-level layout design into multiple sub-divided conductor portions based on conversion rules corresponding to the physical properties of layers for the integrated circuit described in a technology file. The computing system can generate a physical layout design of the integrated circuit from the device-level layout design having the sub-divided conductor portions based on the technology file. The computing system can extract electrical representations of nets corresponding to the conductors in the physical layout design to form a netlist for the physical layout design."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Conductor subdivision in physical integrated circuit layout for parasitic extraction","description":"A computing system can perform a layout-to-schematic process on a geometric layout design of an integrated circuit, which can generate a device-level layout design for the integrated circuit. The comp","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11250196","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11250196","citation_suggestion":"Patentable. \"Conductor subdivision in physical integrated circuit layout for parasitic extraction\" (US-11250196). https://patentable.app/patents/US-11250196","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11250196","json":"https://patentable.app/api/llm-context/US-11250196","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T15:56:02.873Z"}