{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11250921","patent":{"patent_number":"US-11250921","title":"Programming and verifying method for multilevel memory cell array","assignee":null,"inventors":[],"filing_date":"2020-10-14T00:00:00.000Z","publication_date":"2022-02-15T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":7,"abstract":"A programming and verifying method for a multi-level memory cell array includes following steps. In a step (a1), a first row of the multi-level memory cell array is set as a selected row, and A is set as 1. In a step (a2), memory cells in the selected row excluding the memory cells in the target storage state and bad memory cells are programmed to the A-th storage state. In a step (a3), if A is not equal to X, 1 is added to X and the step (a2) is performed again. In a step (a4), if A is equal to X, the program cycle is ended. In the step (a2), the first-portion memory cells of the selected row are subjected to plural write actions and plural verification actions until all of the first-portion memory cells reach the A-th storage state."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Programming and verifying method for multilevel memory cell array","description":"A programming and verifying method for a multi-level memory cell array includes following steps. In a step (a1), a first row of the multi-level memory cell array is set as a selected row, and A is set","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11250921","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11250921","citation_suggestion":"Patentable. \"Programming and verifying method for multilevel memory cell array\" (US-11250921). https://patentable.app/patents/US-11250921","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11250921","json":"https://patentable.app/api/llm-context/US-11250921","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T13:15:47.313Z"}