{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11251080","patent":{"patent_number":"US-11251080","title":"Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits","assignee":null,"inventors":[],"filing_date":"2020-04-14T00:00:00.000Z","publication_date":"2022-02-15T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":14,"abstract":"Techniques herein include methods for fabricating three-dimensional (3D) logic or memory stack integrated with 3D metal routing. The methods can include stacking metal layers within existing 3D silicon stacks. A first portion can be masked while a second, uncovered portion is etched. Predetermined layers in a bottom portion (disposed closer to the substrate) of the multilayer stack can be replaced with a conductor. The second portion can be masked while the first portion is uncovered and processed. This can enable higher density 3D circuits by having multiple metal lines contained within a multilayer 3D nano-sheet. Advantageously, this facilitates easier connections for 3D logic and memory. Moreover, better speed performance can be achieved by having reduced distance for signals to travel to transistor connections."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits","description":"Techniques herein include methods for fabricating three-dimensional (3D) logic or memory stack integrated with 3D metal routing. The methods can include stacking metal layers within existing 3D silico","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11251080","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11251080","citation_suggestion":"Patentable. \"Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits\" (US-11251080). https://patentable.app/patents/US-11251080","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11251080","json":"https://patentable.app/api/llm-context/US-11251080","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T18:55:58.718Z"}