{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11251154","patent":{"patent_number":"US-11251154","title":"Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration","assignee":null,"inventors":[],"filing_date":"2020-05-19T00:00:00.000Z","publication_date":"2022-02-15T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":23,"abstract":"A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration","description":"A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulatin","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11251154","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11251154","citation_suggestion":"Patentable. \"Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration\" (US-11251154). https://patentable.app/patents/US-11251154","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11251154","json":"https://patentable.app/api/llm-context/US-11251154","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T11:55:28.647Z"}