{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11256844","patent":{"patent_number":"US-11256844","title":"Cell row arrangement in regions of integrated circuit layout","assignee":null,"inventors":[],"filing_date":"2020-09-18T00:00:00.000Z","publication_date":"2022-02-22T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","H01L","G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"A method of generating a layout design of an integrated circuit. The method includes forming a first region having at least two first-type cell rows extending in a first direction. Each one of the first-type cell rows has a first row height measured along a second direction perpendicular to the first direction. The method also includes forming a second region having at least two second-type cell rows extending in the first direction. Each one of the second-type cell rows has a second row height measured along the second direction. The first region is adjacent to the second region, and the first row height of the first-type cell rows is different from the second row height of the second-type cell rows."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Cell row arrangement in regions of integrated circuit layout","description":"A method of generating a layout design of an integrated circuit. The method includes forming a first region having at least two first-type cell rows extending in a first direction. Each one of the fir","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11256844","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11256844","citation_suggestion":"Patentable. \"Cell row arrangement in regions of integrated circuit layout\" (US-11256844). https://patentable.app/patents/US-11256844","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11256844","json":"https://patentable.app/api/llm-context/US-11256844","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T06:51:52.197Z"}