{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11257560","patent":{"patent_number":"US-11257560","title":"Test architecture for die to die interconnect for three dimensional integrated circuits","assignee":null,"inventors":[],"filing_date":"2017-09-27T00:00:00.000Z","publication_date":"2022-02-22T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":9,"abstract":"A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR)."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Test architecture for die to die interconnect for three dimensional integrated circuits","description":"A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift r","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11257560","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11257560","citation_suggestion":"Patentable. \"Test architecture for die to die interconnect for three dimensional integrated circuits\" (US-11257560). https://patentable.app/patents/US-11257560","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11257560","json":"https://patentable.app/api/llm-context/US-11257560","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T12:25:54.575Z"}