{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11257738","patent":{"patent_number":"US-11257738","title":"Vertically stacked transistor devices with isolation wall structures containing an electrical conductor","assignee":null,"inventors":[],"filing_date":"2017-12-27T00:00:00.000Z","publication_date":"2022-02-22T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":25,"abstract":"An integrated circuit structure comprises a lower device layer that includes a first structure comprising a first set of transistor fins and a first set of contact metallization. An upper device layer is bonded onto the lower device layer, where the upper device layer includes a second structure comprising a second set of transistor fins and a second set of contact metallization. At least one power isolation wall extends from a top of the upper device layer to the bottom of the lower device layer, wherein the power isolation wall is filled with a conductive material such that power is routed between transistor devices on the upper device layer and the lower device layer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Vertically stacked transistor devices with isolation wall structures containing an electrical conductor","description":"An integrated circuit structure comprises a lower device layer that includes a first structure comprising a first set of transistor fins and a first set of contact metallization. An upper device layer","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11257738","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11257738","citation_suggestion":"Patentable. \"Vertically stacked transistor devices with isolation wall structures containing an electrical conductor\" (US-11257738). https://patentable.app/patents/US-11257738","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11257738","json":"https://patentable.app/api/llm-context/US-11257738","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T15:03:44.914Z"}