{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11257823","patent":{"patent_number":"US-11257823","title":"Semiconductor device having vertical transistors and method of forming same","assignee":null,"inventors":[],"filing_date":"2018-07-30T00:00:00.000Z","publication_date":"2022-02-22T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":11,"abstract":"The disclosed technology generally relates to semiconductor devices, and more particularly to a static random access memory (SRAM) having vertical channel transistors and methods of forming the same. In an aspect, a semiconductor device includes a semiconductor substrate and a semiconductor bottom electrode region formed on the substrate and including a first region, a second region and a third region arranged side-by-side. The second region is arranged between the first and the third regions. A first vertical channel transistor, a second vertical channel transistor and a third vertical channel transistor are arranged on the first region, the second region and the third region, respectively. The first, second and third regions are doped such that a first p-n junction is formed between the first and the second regions and a second p-n junction is formed between the second and third regions. A connection region is formed in the bottom electrode region underneath the first, second and third regions, wherein the connection region and the first and third regions are doped with a dopant of a same type. A resistance of a path extending between the first and the third regions through the connection region is lower than a resistance of a path extending between the first and the third regions through the second region. A second aspect is a method of forming the semiconductor device of the first aspect."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor device having vertical transistors and method of forming same","description":"The disclosed technology generally relates to semiconductor devices, and more particularly to a static random access memory (SRAM) having vertical channel transistors and methods of forming the same. ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11257823","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11257823","citation_suggestion":"Patentable. \"Semiconductor device having vertical transistors and method of forming same\" (US-11257823). https://patentable.app/patents/US-11257823","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11257823","json":"https://patentable.app/api/llm-context/US-11257823","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T08:30:33.706Z"}