{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11263011","patent":{"patent_number":"US-11263011","title":"Compound instruction set architecture for a neural inference chip","assignee":null,"inventors":[],"filing_date":"2018-11-28T00:00:00.000Z","publication_date":"2022-03-01T00:00:00.000Z","cpc_codes":["G06F","G06N","G06F","G06F","G06F","G06F","G06F","G06N","G06N","G06N"],"num_claims":20,"abstract":"A device for controlling neural inference processor cores is provided, including a compound instruction set architecture. The device comprises an instruction memory, which comprises a plurality of instructions for controlling a neural inference processor core. Each of the plurality of instructions comprises a control operation. The device further comprises a program counter. The device further comprises at least one loop counter register. The device is adapted to execute the plurality of instructions. Executing the plurality of instructions comprises: reading an instruction from the instruction memory based on a value of the program counter; updating the at least one loop counter register according to the control operation of the instruction; and updating the program counter according to the control operation of the instruction and a value of the at least one loop counter register."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Compound instruction set architecture for a neural inference chip","description":"A device for controlling neural inference processor cores is provided, including a compound instruction set architecture. The device comprises an instruction memory, which comprises a plurality of ins","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11263011","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11263011","citation_suggestion":"Patentable. \"Compound instruction set architecture for a neural inference chip\" (US-11263011). https://patentable.app/patents/US-11263011","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11263011","json":"https://patentable.app/api/llm-context/US-11263011","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T20:35:55.539Z"}