{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11263147","patent":{"patent_number":"US-11263147","title":"Memory system including logical-to-physical address translation table in a first cache and a compressed logical-to-physical address translation table in a second cache","assignee":null,"inventors":[],"filing_date":"2019-09-06T00:00:00.000Z","publication_date":"2022-03-01T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":11,"abstract":"According to one embodiment, a memory system stores a part of a logical-to-physical address translation table stored in a nonvolatile memory, as a first cache, in a random-access memory, and stores a compressed logical-to-physical address translation table obtained by compressing the logical-to-physical address translation table, as a second cache, in the random-access memory. The memory system stores first information indicative of a part of a first address translation data, in a first area of a first entry of the second cache where first compressed address translation data is stored. When executing processing of checking a part of the first address translation data, the memory system refers to the first information stored in the first entry of the second cache."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory system including logical-to-physical address translation table in a first cache and a compressed logical-to-physical address translation table in a second cache","description":"According to one embodiment, a memory system stores a part of a logical-to-physical address translation table stored in a nonvolatile memory, as a first cache, in a random-access memory, and stores a ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11263147","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11263147","citation_suggestion":"Patentable. \"Memory system including logical-to-physical address translation table in a first cache and a compressed logical-to-physical address translation table in a second cache\" (US-11263147). https://patentable.app/patents/US-11263147","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11263147","json":"https://patentable.app/api/llm-context/US-11263147","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T21:21:39.525Z"}