{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11263380","patent":{"patent_number":"US-11263380","title":"Failsafe circuit, layout, device, and method","assignee":null,"inventors":[],"filing_date":"2018-12-31T00:00:00.000Z","publication_date":"2022-03-01T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":20,"abstract":"A circuit includes a reference node configured to carry a reference voltage level, a first node configured to carry a signal having a first voltage level or the reference voltage level, a second node configured to carry a power supply voltage having a power supply voltage level in a power-on mode and the reference voltage level in a power-off mode, and a plurality of transistors coupled in series between the first node and the reference node. Each transistor of the plurality of transistors receives a corresponding control signal of a plurality of control signals, and each control signal has a first value based on the power supply voltage in the power-on mode and a second value based on the signal in the power-off mode."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Failsafe circuit, layout, device, and method","description":"A circuit includes a reference node configured to carry a reference voltage level, a first node configured to carry a signal having a first voltage level or the reference voltage level, a second node ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11263380","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11263380","citation_suggestion":"Patentable. \"Failsafe circuit, layout, device, and method\" (US-11263380). https://patentable.app/patents/US-11263380","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11263380","json":"https://patentable.app/api/llm-context/US-11263380","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T09:22:50.082Z"}