{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11264110","patent":{"patent_number":"US-11264110","title":"Refresh operations for memory cells based on susceptibility to read errors","assignee":null,"inventors":[],"filing_date":"2020-02-13T00:00:00.000Z","publication_date":"2022-03-01T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"Apparatuses and techniques are described for periodically refreshing word line voltages in a block of memory cells based on the susceptibility of the block to read errors. One source of read errors is delayed read disturb which results from a low word line voltage during idle periods of the memory device. In one aspect, periodic refresh operations are optimized based on factors such as a number of bits per cell in the block and number of program-erase (P-E) cycles. For example, at high P-E cycles, the amplitude of a refresh voltage for a single-level cell (SLC) block can be 0 V or lower while the amplitude of a refresh voltage for a multi-level cell (MLC) block can be an intermediate voltage between 0 V and a pass voltage."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Refresh operations for memory cells based on susceptibility to read errors","description":"Apparatuses and techniques are described for periodically refreshing word line voltages in a block of memory cells based on the susceptibility of the block to read errors. One source of read errors is","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11264110","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11264110","citation_suggestion":"Patentable. \"Refresh operations for memory cells based on susceptibility to read errors\" (US-11264110). https://patentable.app/patents/US-11264110","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11264110","json":"https://patentable.app/api/llm-context/US-11264110","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T17:06:38.270Z"}