{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11264278","patent":{"patent_number":"US-11264278","title":"Transistor with reduced gate resistance and improved process margin of forming self-aligned contact","assignee":null,"inventors":[],"filing_date":"2020-08-11T00:00:00.000Z","publication_date":"2022-03-01T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","B82Y","H01L"],"num_claims":19,"abstract":"The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes two gate structures, a first conductor, a barrier, a second conductor and a plurality of air gaps. The two gate structures are located on a surface of a semiconductor material substrate. The first conductor is disposed between the two gates structures. The barrier is disposed between the first conductor and the gate structure. The second conductor is disposed on the first conductor. The air gaps are disposed at two sides of the second conductor. A width of the second conductor is greater than a width of the first conductor."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Transistor with reduced gate resistance and improved process margin of forming self-aligned contact","description":"The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes two gate structures, a first conductor, a barrier, a s","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11264278","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11264278","citation_suggestion":"Patentable. \"Transistor with reduced gate resistance and improved process margin of forming self-aligned contact\" (US-11264278). https://patentable.app/patents/US-11264278","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11264278","json":"https://patentable.app/api/llm-context/US-11264278","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T22:14:56.292Z"}